1. Field of the Invention
The invention generally relates a SRAM device having at least one vertical SRAM cell comprising vertical transistors to reduce the memory cell size. In particular, the invention relates to a SRAM device having at least one vertical SRAM cell comprising at least four vertical transistors.
2. Description of Related Arts
U.S. Pat. No. 5,576,238 refers to one species of SRAM cells including four transistors and two resistors (4T/2R), which is slow and consumes high power. The embodiment shown in its FIG. 7 has two vertical transistors formed above the resistors, which are in turn formed above two regular transistors grown on the substrate. There is no vertical transistor above any other vertical transistors.
U.S. Pat. No. 5,341,327 tried to reduce the cell size problem by adopting all thin film transistors (“TFT”) in a six-transistor (6T) SRAM cell, which circuit chart is shown in its FIG. 36. As shown in its FIG. 5, a pair of transfer transistors Q3 and a pair of driver transistors Q1 are provided, which are constituted with n-type TFTs. A pair of p-type load transistors Q5 is formed on the surface of the interlayer insulation layer. The TFT 6T SRAM cell is smaller than the 4T/2R SRAM cell but still slow.
U.S. Pat. No. 5,198,683 further reduces the cell area by providing a pair of load TFTs having a vertical channel along with the other four regular transistors within a six-transistor (6T) SRAM cell. However, the vertical load TFTs are located in the same layer as the other four regular TFTs such that the sources and drains of the vertical load TFTs inevitably bent horizontally. As such, the size-reducing effect of this structure is relatively limited by its one-layer structure. U.S. Pat. No. 6,309,930 shares the same problem. As shown in its FIG. 4, the ends of the drain and sources 4S/D1, 4S/D2 of the 4th transistor bent horizontally.
For a totally different purpose from reducing the cell size, i.e., to reduce one wiring layer, JP Pat. App. No. 09-232447 adopts a vertical channel structure for one TFT so as to share the substrate as a wiring layer between the gate electrode of the vertical TFT with another regular transistor in its FIG. 7D. Incidentally, a vertical source and a vertical drain are provided to work in conjunction with a vertical channel. The reference merely suggests applying a pair of the vertical TFTs as load transistors in the same layer with the other four regular transistors to form a SRAM cell.
A bulk 6T SRAM cell has six transistors grown in a bulk semiconductor substrate, such as single crystal silicon. A 6T bulk SRAM cell is faster than the 4T/2R SRAM cell or the 6TFT SRAM cell. It is often fabricated in CMOS (complementary metal oxide semiconductor) technology with four of the transistors being n-channel devices while the remaining two transistors are p-channel devices. This 6T configuration offers several advantages including operating at a low level of power and at a high speed. However, 6T SRAM cells utilizing transistors formed in a bulk substrate consume a large area since the bulk transistors are formed next to one another in the substrate and are essentially in the same plane. As such, it is difficult to fabricate the conventional bulk 6T SRAM to a high density.
U.S. Pat. No. 6,204,518 B1 reduces the bulk 6T SRAM cell size by stacking a pair of load transistors Q3 and Q4 above a pair of drive transistors Q1 and Q2 as well as a pair of transfer transistors Q5 and Q6. The respective circuit diagram and a cross sectional view of the structure are provided in its FIG. 1. U.S. Pat. No. 6,271,542 B1 and Ser. No. 2001/0028059 A1 take the same approach.
PCT/JP99/02505 discloses a pair of PLED devices to be incorporated in a flip-flop; nonvolatile 6T SRAM cell as in its FIG. 1. As shown in the cross sectional view of the PLED device in its FIG. 3, the insulation layers 708, 709, and 710 are provided between the source 701 and the drain 700 to reduce the leakage current to a substantially zero value. The PLED device is merely designed as an external device to the 6T SRAM cell.
U.S. Pat. No. 6,229,161 is directed to another species of SRAM cells including a negative differential resistance (“NDR”) device coupled with a NMOS transistor (only two elements: 1T/1R) such that it takes less space than a 6T SRAM cell. In its FIG. 6, the NDR device with a thin vertical PNPN structure is coupled with a vertically-arranged NMOS. Since one of the drain and the source of the NMOS transistor are grown in the substrate, it bents horizontally.
Currently, there is a demand to further reduce the low-power SRAM cell size than the prior art structures so as to accommodate more compact cellular phones, PDAs, and other mobile devices.